Back-end Design & Simulation Capabilities
Some of our areas we engage in:
- Chip Assembly, Floorplanning & Top-level Layout
- Block-level layout
- Design Verification (DRC, ERC, QRC, LVS)
- Synthesis & Timing Analysis
- Digital Place & Route
- Block & Top-level Functional Simulations
- Block-level & Top-Level AMS Verification
- Block & Top-level Parasitic Extracted Simulations